In the fabrication of specialized integrated circuits (ICs) such as custom ICs, gate arrays, or application specific integrated circuits (ASICs), it is an advantage to be able to build such circuits rapidly and accurately for the customer. Typically, the custom IC or ASIC customer has a need for the circuit to be delivered quickly. However, since the fabrication of a typical IC may take weeks, there is a need to shorten the time it takes to deliver such circuits to the custom IC or ASIC customer. That is, it is necessary to reduce the cycle time from the custom or ASIC order and the delivery of the finished product to the customer.
The ASIC cycle time can be reduced in many ways. One technique is to build and have on hand unfinished ICs that can be customized by changes in the later processing steps so that the customer need not wait for the performance of the earlier processing steps. This procedure is commonly followed in the formation of the metallization or interconnect layer which joins various preformed circuit elements such as field effect transistors (FETs), capacitors and resistors. In the fabrication of custom gate arrays, this procedure is particularly common.
Heretofore the basic characteristics of the FETs in the partially finished IC are set early in the process since the primary working elements of the FET, the source, drain and channel, are formed within the semiconductor substrate. Usually, the substrate elements are covered by multiple layers of dielectric or conductive material and the elements buried thereby cannot be changed, except with great difficulty.
As very large scale integration (VLSI) processes are used to make FETs, the channel lengths become shorter and gate oxides become thinner, and a higher doping level under the gate in the channel region is required to provide the desired threshold and subthreshold voltage characteristics. Employing a heavily doped substrate will provide this higher channel doping level; however, such a condition increases the back-gate bias sensitivity of the threshold voltage and tends to increase the source/drain-to-substrate capacitances as well. A shallow ion implant is widely used to set the desired doping level in the channel region without increasing the background substrate doping level. By this technique, the threshold sensitivity to back-gate bias can be minimized while still having the desired high surface concentration. See, for example, S. M. Sze, VLSI Technology, McGraw-Hill, 1983, pp. 468-470.
However, as explained, the partially completed ICs typically have the sources, channels, drains, and at least the polysilicon gate layer in place before customization begins. At this point in the process, however, it would be difficult to perform a channel implant to affect the threshold voltage of the device. Thus, it would be advantageous if a process could be discovered by which the threshold voltage of a FET could be adjusted relatively late in the fabrication process for custom and application specific ICs. In summary, the V.sub.T adjustment is usually performed by ion implantation prior to gate definition, which causes a longer turn around time for processing custom circuits after the order is received.
It is known in the art that the threshold voltage, V.sub.T, of a FET can be modified by using a semiconductor material as the gate material and varying the doping concentration of the gate. For example, polycrystalline silicon (polysilicon) doped with n-type or p-type impurities could be used. Refractory metals, such as molybdenum, titanium, tungsten, and tantalum and their silicides have been used in conjunction with polysilicon or alone to reduce the resistance of the gate materials. The technique of combining a refractory metal silicide on top of doped polysilicon, sometimes called polycide, has the advantage of preserving the well-understood polysilicon/SiO.sub.2 interface while lowering the overall sheet resistance of the polycide. It is also known that employing certain silicides directly on the gate oxide can result in larger work functions than using n.sup.+ -doped polysilicon alone, and that corresponding adjustments in the channel-doping procedure may be required.
It is also known that the dopants in polysilicon, such as boron and arsenic, can diffuse extremely rapidly in some refractory metal silicides that are contacted with the polysilicon during anneal. The dopants may subsequently diffuse out of the silicide into adjacent polysilicon where the concentration of that dopant is relatively less. It is also known that if such rapid diffusion occurs in a polysilicon gate line that the threshold voltages of the device can be adjusted to compensate for the effect. See, for example, L. C. Parrillo, et al., "A Fine-Line CMOS Technology that Uses p.sup.+ Polysilicon/Silicide Gates for NMOS and PMOS Devices," IEDM Technical Digest, 1984, pp. 418-421.